How to prevent serious defect incident in 5nm, 7nm, 10nm fabs?
  From news report, Samsung and TSMC are expected to enter 5nm process mass production in 2020. The competition on 5nm wafer yield and market share will be very intense. ESI’s brand new OpenShortPlatform, including two crucial technologies “Smart defect screen and sample technology” and “Defect size metrology technology”, can discover various types of tiny yield loss defects in 5nm process and enhance 5nm wafer yield.

Rebuilding a better solution for inline wafer inspection
  There are more than hundred process steps and equipments used in 5nm, 7nm, and 10nm fabs.Defect incidents impact wafer yield and revenue loss when equipment mal-function, or material problem happens. By TSMC press news of 2019.02.15 and other news reports, photoresist incident caused enormous numbers of 12/16 nm wafers scrapped and US$550 million revenue reduction. material problem.This photoresist incident belongs to TSMC has taken action to strengthen its inline wafer inspection
  Medium scale defect incidents will happen more often in 5nm, 7nm, and 10nm fabs because the process and defect complexity are significantly higher than 12/16nm fabs. The accumulated loss for several medium scale defect incidents might not be less than the loss in a serious photoresist incident. So, facing severe challenge on smaller geometry 5nm, 7nm, and 10nm production, the most urgent action should be rebuilding a better solution for inline wafer inspection.

To prevent serious defect incident in 5nm, 7nm, 10nm fabs, you need to know what is the most critical factor.
  Normal wafer inspection and defect sample selection procedures are described below.
1.Lot and wafer sample selection for inline defect inspection:
 i.For every ten lots, two lots are selected for inline defect inspection
 ii. For each lot (25 wafers), two to three wafers are selected for inline defect inspection
 iii. For each wafer defect inspection, it could be full wafer defect inspection, half wafer defect inspection, or one third wafer defect inspection.
 iv. Regular defect count range is between 1000 and 50000.For smaller geometry dimension, defect count is increased.
2.Defect sample selection:Due to slow throughput in Review SEM,the regular number of defect samples fall between 50 and 200.
  The wafer yield improvement process is described below.
Step 1: Defect inspection -> Step 2: Defect analysis platform to pick defect sample to take SEM images -> Step 3: Review SEM -> Step 4: Root cause analysis.Since bad defects directly impact wafer yield. The discovery of bad defects is dependent upon the defect analysis platform in step 2.Then, the fab is able to dig out root causes of bad defects and improve yield afterward. So, the most critical factor in 5nm, 7nm, and 10nm wafer yield is the capability of defect analysis platform. Likewise, the most critical factor to prevent 5nm, 7nm, and 10nm serious defect incident is also the capability of defect analysis platform.

How to win wafer yield and prevent serious defect incident in 5nm,7nm, 10nm fabs
  Very often Fabs suffer big issue in discovering bad defects in advanced technology. ESI’s invention patent, Method for smart defect screen and sample, maps inline defect to corresponding IC design layout and performs Critical Area Analysis to classify nuisance defect and killer defect. The breakthrough is this smart defect screen and sample platform can identify and filter nuisance defects accurately. The basic concept in ESI’s invention is “The more nuisance defects to be filtered accurately,the more bad defects to be discovered.”
  Another big issue suffered most in wafer yield improvement is defect size metrology. Nuisance defects are falsely classified into high risk killer defects because of incorrect defect size measurement results. ESI’s defect size metrology solution successfully improves wafer yield by providing correct defect size.
  ESI OpenShortPlatform, including smart defect screen technology and ESI’s defect size metrology solution, has distinguished itself in the race for 5nm, 7nm, and 10nm win. More than that, ESI OpenShortPlatform will perform as the guardian to prevent serious defect incident in 5nm, 7nm, and 10nm fabs.
  To summarize, smart defect analysis platform is a prime and must selection tool for yield enhancement in semiconductor industry. After the detailed prior art search, Gainia Inc., the intelligent asset services at ITRI, pointed out that ESI’s patent invention ”Method for smart defect screen and sample (US 8312401、CN1614876、ROC I402928)” is the founder of Artificial Intellegence defect analysis in the world. Based on that invention, ESI OpenShortPlatform is one of a kind in the industry.